Interesting way to look at it but at a very simple level, I guess that's true. Keep in mind these are transistors that flip on and off. There is no analog circuitry there ... with CMOS, you have 2 transistors an n-mos and a p-mos that switch in series. But in any case, you have thousands and thousands of these transistors charging discharging ... if you increase the frequency, you have a lot of such charge/discharges ... when you increase voltage, the level of charge discharge is higher Just keep in mind that typically only 1 to 0 transitions consume power!!! 0 - 0 transition doesn't need power 1 - 1 transition doesn't need power 0 - 1 doesn't need power but I think I am over simpifying. In any case, if you can create a number system or some special transformation on your computatinos that reduces 1-0 transitions, then you can save a lot of power while computing!!! As an example, in a lot of DSP chips where you deal with a lot of - and + numbers, they use special encoding to represent numbers since -1.0 is usually 1111111 and 0.0 is 0000000 and anytime you go from mathematical -1 to 0 in a computation (usually a lot) you flip a LOT of bits and that's not good.