Microchips and Digital Stuff

[DominO123]

BTW, what happened with the Power4 chip? It was supposed to be a revolution by its size and power consuption...

[Sip]

Power4 was pretty sweet and it is very interesting what kinds of barriers we are getting to ... for example, now the "leakage" current of the transistors in the chip are becoming significant source of power consumption where as before that was not really an issue. So what that means is that a "transistor" is not a free commodity on the chip ... every transistor you add, you make the power consumption worse even if that part of the chip is not clocked (isn't running anything) .. with quantum effects and tunneling and leakage effects there is already a lot of power discipated (wasted). You can start watercooling chips but the power levels go up very fast with not much gained in terms of performance.

 

So you can go from 100W power discipation to 160W with just 5% gain in performance... you can still cool the 160W with water but that obviously doesn't justify the cost with only 5% gain in performance.

 

Anyway, Power4 got passed by the much much cheaper AMD in a couple of months! Even though at the time it came out, it was the best in terms of the specint and some other benchmarks.

 

BUT

 

This is the latest rumor now .. that Microsoft just signed a deal with IBM to design the next generation XBOX around the power4 core

[DominO123]

hmmm... I know my answer sounds dumb, but if it is so much trouble, why not building processors by including two processors in one chip, in order to make it run in parallel... I mean, would that not fix in a way the problem, by making it run 1/2 or 2/3 of the clock speed of just one? Edited November 8, 2003 by Fadix

[Sip]

Not that simple

 

If you look at some of the more modern processors, you have what is called a "pipelined" architecture ... this means that each instruction that comes in is split into bunch of smaller steps and each of those steps is executed in one cycle. So while you are decoding the current instruction, you can be fetching the next one from memory and already executing the one before it ...

 

In other words the entire instruction execution (fetch, decode, execute, write back to memory) may take several clock cycles from beginning to end. But on average you can get 1 instruction per cycle by pipelining (interleave execution). But if there is a "branch" in your program, then you have to flush the pipeline and go bring the insturctions starting from the branch address .. the ones you had brought before are wrong ones!

 

So long pipelines will let you reduce your clock cycle (faster clock) since you are doing less things per clock ... but you have a big penalty of several clock cycles every time there is a branch of any kind in the code.

 

NOW on top of this ...

 

Processors have multiple execusion units like multiple integer adder/subtractors, several multipliers and dividers, floating point units etc. So they can execute several instructions in parallel. On top of that, they may support out of order execution of instructions and even do sophisticated branch prediction to minmize pipeline flush penalty.

 

For example, while you are executing a lengthy double precision floating point division, you can bring in and do a bunch of integer additions etc in parallel to that in the processor.

 

Anyway, what I am trying to tell you, is that modern processors like Pentium4 are highly paralellized inside and not to mention even features like hyperthreading that allow you to do a lot of parallel things.

 

 

 

The problems I am talking about above are physical limitations of CMOS and the manufacturing processes. By shrinking the devices (smallest transistors) and their connections, you are increasing the resistance in the wires, and have a smaller area but at the same time are pumping up the frequency (for performance). Then you have leakages and other effects that are increasing as the gate and oxide thicknesses of the chip are decreasing ... so you are forced to reduce the voltage to be able to keep the power discipation in check. Anyway, I don't want to throw too much technical jargon into this unless you are interested ... but in terms of "parallel" processing, the CPUs are doing a pretty good job of that ... as much as a program can be parallelized anyway on eacy CPU.

 

Now if you are talking about desinging special multi-processor systems, that's a diffferent story and now you have to have operating system, compiler, and application support to take advantage of that. But that will not get around each processors limitations and will not make your system run 2x as fast as single processor with 2 processors!

[DominO123]

hmmm ... I know this is becoming too technical, but I had this question in mind... why reducing the voltage to reduce the power consuption, when technically it is the Intensity that should be responsable of the heat dissipation? Edited November 8, 2003 by Fadix

[Sip]

Your power consumption on a digital chip has an equation of the following form:

 

P = P_static + P_short + P_dynamic + P_glitching

 

The static power is the power waste through leakages. That is pretty low these days.

 

P_short is when the CMOS gate is switching ... that is also not that much with good manufacturing techniques.

 

Forget about glitching power for now.

 

Most power goes to dymanic power consumption (when chip is running)

 

P_dynamic = C * f * V^2

 

C is the capacitance of the part of the circuit switching. There are ways to fix that but just think of it as an attribute of a given design for now.

 

So now you see, frequency and Voltage directly impact power consumption. Frequency dependence is linear while Voltage is quadratic. So by increasing frequency, you are increasing the dynamic power consumption. By reducing the voltage, you are reducing the dynamic power consumption.

 

However, when you reduce voltage, your signals are more susseptible to thermal and other noise. So you can't just reduce voltage and increase frequency and expect your chip will operate properly. You can sometimes do dynamic voltage scaling and frequency stepping ... like in a laptop you can run it faster for most performance (more power consumed) or slower (for longer battery life). This is also the reason that with overclocking, you have to step up the core voltage on the CPU to be stable ... but now you must cool the chip in order to prevent it from burning up with much more power discipation (both freq and voltage are up with overclocking).

 

Hope this answers your question.

[DominO123]

I realised that my question was stupid... I guess the intensity is reduced more the chip get smaller, and the intensity is dependent of the total chip resistance... so that would leave the electrical potential as the main variable, taking in account your presented total power consuption... The goal would be to reduce the internal resistance, that would require less voltage, and as a result, less heat dissipation... and to be able to reduce the voltage, we are forced to reduce the size while trying to not increase the resistance that would be cause by the reduction of the size etc... ashjh%?%#F76%#... you just overloaded my brain.... so I think I will go to bed now.

[Sip]

Interesting way to look at it but at a very simple level, I guess that's true.

 

Keep in mind these are transistors that flip on and off. There is no analog circuitry there ... with CMOS, you have 2 transistors an n-mos and a p-mos that switch in series. But in any case, you have thousands and thousands of these transistors charging discharging ... if you increase the frequency, you have a lot of such charge/discharges ... when you increase voltage, the level of charge discharge is higher

 

Just keep in mind that typically only 1 to 0 transitions consume power!!!

 

0 - 0 transition doesn't need power

1 - 1 transition doesn't need power

0 - 1 doesn't need power but I think I am over simpifying.

 

In any case, if you can create a number system or some special transformation on your computatinos that reduces 1-0 transitions, then you can save a lot of power while computing!!!

 

As an example, in a lot of DSP chips where you deal with a lot of - and + numbers, they use special encoding to represent numbers since -1.0 is usually 1111111 and 0.0 is 0000000 and anytime you go from mathematical -1 to 0 in a computation (usually a lot) you flip a LOT of bits and that's not good.

[DominO123]

Interesting stuff When they charge and discharge, I guess by charging they make power a little less avelable for others naar them, and when they do discharge, they can overload some others? Is that why that is supposed to be a problem? I mean, is that one of the way more those transistors come closer with each others(by reducing the size of the chip), more by their charging and discharging will influence other transistors more closer to them, by reducing and increasing the quantity of charge avelable each time they charge and discharge?

[Sip]

Domino, I thought you may find this interesting, although the title of the article is just stupid ...

 

Intel's Montecito Chip to Run Multiple Applications

 

... The company has already said the chip will have two processors on a single piece of silicon, known as "dual core" and have 24 megabytes of cache.

 

not too bad eh? 24MB of cache!!!! But the "dual core" thing is doing exactly what you were talking about with multiple processors.

[DominO123]

Sip dude, DON'T EVER DO THAT TO ME AGAIN When I saw that thread, I FREAKED OUT! Thinking I was suffering from total amnesia... I was sure to not have started a thread titled like that... wondered wondered... and finally decided to open it...

 

Oh, interesting link BTW.

Edited November 14, 2003 by Fadix